1. Field of the Invention
The present invention relates to ferroelectric integrated circuit memory devices, and more particularly to apparatus and methods for testing such memories.
2. Statement of the Problem
It has been known since at least the 1950""s that if a practical ferroelectric memory could be made, it would provide a fast, dense, non-volatile memory that could be operated at relatively low voltages. See Orlando Auciello et al., xe2x80x9cThe Physics of Ferroelectric Memoriesxe2x80x9d, Physics Today, July 1998, pp. 22-27. The principal type of ferroelectric memory being explored today is a non-volatile ferroelectric random access memory in which each memory cell contains at least one ferroelectric capacitor and at least one switch. These are referred to by several different acronyms, such as NVRAM, FeRAM, FRAM, and FERAM. We shall refer to such memories as FERAMS herein. However, other ferroelectric memories are also known, such as memories in which each memory cell is a ferroelectric field effect transistor (ferroelectric FET), and memories in which each cell consists of a single ferroelectric capacitor, sometimes referred to as a xe2x80x9craw arrayxe2x80x9d or cross point array because it is simply an array formed by rows and columns or conductors with a ferroelectric between the conductors where they cross. See, for example, J. R. Scott, C. A. Paz De Araujo, and L. D. McMillan, xe2x80x9cIntegrated Ferroelectricsxe2x80x9d, in Condensed Matter News, Vol. 1, No. 3, pp. 15-20, 1992 for a discussion of the ferroelectric FET, and U.S. Pat. No. 4,707,897 issued to George A. Roher and Larry McMillan on Nov. 24, 1987, for a discussion of the raw array. Some projections suggest that the market for ferroelectric memories may be about ten billion dollars by the year 2002. See xe2x80x9cA Computer In Every Shirt Collarxe2x80x9d, Forbes, Mar. 8, 1999.
Non-volatile memories, such as ferroelectric memories, should be able to retain data for at least ten years under worst case conditions, such as elevated temperature and repeated pulsing and/or switching of a single memory cell. In the last few years, substantial progress has been made in overcoming historical problems of failure of ferroelectric memories, such as ferroelectric fatigue. See Auciello et al., Supra, at pp. 23-25. However, in all memories, including ferroelectric memories, individual memory cells may fail prematurely. Some of the failure mechanisms of ferroelectric memories, such as defects in the transistor or transistors associated with each memory cell, e.g. anomalously shifted threshold voltage or anomalously shifted transistor gain, and defects in passive devices, such as anomalous contact window resistance, anomalous leakage current, insulator dielectric breakdown, and inadequate isolation between electronic devices, are related to failure mechanisms in conventional memories, such as dynamic random access memories (DRAMS). However, other failure mechanisms in ferroelectric memories, such as anomalous ferroelectric fatigue, anomalous imprinting, and anomalous shifting of parameters such as coercive voltage and polarizability, are unique to ferroelectric memories. Since these are also the failure mechanisms for which there is little experience in predicting, it would be highly useful to have apparatus and methods for determining and isolating individual memory cells and/or individual memory chips which will fail prematurely.
One type of test that is often used in testing electronic devices is called a xe2x80x9cmargin testxe2x80x9d. A xe2x80x9cmargin testxe2x80x9d is generally any test which determines circuit weaknesses and potential malfunctions by varying the operating conditions of the circuitry. Typical operating conditions that are varied can include supply voltage and frequency of the applied electronic signal. Margin tests for determining and isolating individual memory cells in conventional electronic memories, such as DRAMS, are well-known. See, for example, U.S. Pat. No. 5,265,056 issued to James E. O""Toole and Robert J. Proebstling on Nov. 29, 1983; U.S. Pat. No. 5,265,056 issued to Edward Butler et al. on Nov. 23, 1993; U.S. Pat. No. 5,610,867 issued to John K. DeBrosse et al. on Mar. 11, 1997; and U.S. Pat. No. 5,825,782 issued to Frankie F. Roohparvar on Oct. 20, 1998. However, no margin test that can isolate failures related to the unique properties of ferroelectric memories has yet been devised.
The invention solves the above problem by providing a margin test, and margin test apparatus, that permits the determination of individual ferroelectric memory cells and individual ferroelectric memory chips which will fail prematurely due to failure mechanisms that are unique to ferroelectric memories. An important aspect of the invention is the application of ferroelectric stress to ferroelectric memory cells in combination with a write and a read process which determines which of the cells may prematurely fail. In another key aspect, the invention comprises a method of testing an integrated circuit memory device comprising a plurality of memory cells, each cell including a ferroelectric material having a coercive voltage, the method including two or more processes selected from the group consisting of: applying a ferroelectric stress to the memory cells, performing a partial write on said memory cells, heating the memory cells, and performing a partial read of said memory cells. The invention usually comprises other steps also, such as an analysis step in which the results of the test are used to accept, reject, isolate, or repair cells which may be subject to premature failure.
The invention also solves the above problems by providing a ferroelectric memory device that includes circuits for determining which cells may prematurely fail due to failure mechanisms that are unique to ferroelectric memories. The ferroelectric memory device includes a test circuit for applying voltages to memory cells in the memory to perform one or more of the following functions: applying ferroelectric stress to the memory cells; performing a partial write of memory cells; and performing a partial read of memory cells.
The invention provides a method of testing a ferroelectric integrated circuit memory device comprising a plurality of memory cells, each including a ferroelectric material having a coercive voltage, the method comprising: writing a known logic state to the memory cells; applying ferroelectric stress to the memory cells; and reading the memory cells to provide output data indicative of the likelihood of premature failure for each of the memory cells. Preferably, the step of applying ferroelectric stress comprises applying a voltage pulse to the memory cells. Preferably, the step of applying a voltage pulse comprises a step selected from the group consisting of: repeatedly applying to the cells a voltage at or above the coercive voltage, and repeatedly applying to the cells a voltage lower than the coercive voltage. Preferably, the step of applying comprises the step of repeatedly applying to the cells a voltage at or above the coercive voltage and corresponding to a first logic state, and the step of writing comprises writing to a second logic state opposite to the first logic state. Preferably, the step of reading comprises performing a partial read of each of the memory cells. Preferably, the step of performing a partial read comprises a step selected from the group consisting of: reading the cells with a voltage lower than the normal read voltage for the memory cells, placing a read voltage across the ferroelectric material for a period of time that is shorter than the normal read time for the memory cells, and sensing the read output signal with a narrower than normal sense voltage window. Preferably, the memory includes a plurality of plate lines and a plurality of bit lines and the step of reading the cells with a voltage lower than the normal read voltage comprises a step selected from the group consisting of: changing the plate line voltage, and changing the bit line precharge voltage. Preferably, the step of writing comprises writing each of the cells to a first logic state and the step of applying comprises the first step of repeatedly applying to the cells a voltage below the coercive voltage and corresponding to a second logic state different from the first logic state. Preferably, the step of reading the cells to provide output data includes the step of recording the number of the first repetitions required for each of the cells to fail to read the first logic state in the read step. Preferably, the method further includes the steps of rewriting the memory cells to the first logic state, heating the memory cells, a second step of repeatedly applying to the cells a voltage below the coercive voltage and corresponding to a second logic state different than the first logic state, and a second step of reading the cells and recording the number of the second repetitions required for each of the cells to read the first logic state in the second read step. Preferably, the method also includes the step of comparing the number of the first repetitions to the number of the second repetitions and accepting, rejecting or repairing the memory device based on the comparison. Preferably, the method further includes the step of heating the plurality of memory cells. Preferably, the step of writing comprises performing a partial write of each of the memory cells. Preferably, the method further includes the step of accepting, rejecting or repairing the memory device based on the output data.
In another aspect, the invention provides a method of testing a ferroelectric integrated circuit memory device comprising a plurality of memory cells, each including a ferroelectric material, the method comprising: partially writing a known state to the memory cells; heating the memory cells; and reading the memory cells to provide output data indicative of the likelihood of premature failure for each of the memory cells. Preferably, the step of partially writing comprises a step selected from the group consisting of: writing the known value to the cells with a voltage lower than the normal write voltage for the memory cells; placing a write voltage across the ferroelectric material for a period of time that is shorter than the normal write time for the memory cells; and sensing a read output signal with a narrower than normal sense voltage window. Preferably, the step of reading comprises performing a partial read of each of the memory cells.
In a further aspect, the invention provides a method of testing a ferroelectric integrated circuit memory device comprising a plurality of memory cells, each including a ferroelectric material, the method comprising: writing a known state to the memory cells; heating the memory cells; and partially reading the memory cells to provide output data indicative of the likelihood of premature failure for each of the memory cells. Preferably, the step of partially reading comprises a step selected from the group consisting of: reading the cells with a voltage lower than the normal read voltage for the memory cells; placing a read voltage across the ferroelectric material for a period of time that is shorter than the normal read time for the memory cells; and sensing the read output signal with a narrower than normal sense voltage window. Preferably, the step of writing comprises performing a partial write of each of the memory cells.
The invention also provides a ferroelectric integrated circuit memory device comprising: a plurality of memory cells, each of the memory cells including a ferroelectric material; a plurality of conducting lines, each of the lines connected to or connectable to a selected one of the memory cells; a drive circuit for applying a predetermined voltage for a predetermined time to a selected one of the lines, the predetermined voltage and time being the normal voltage and time required to perform a function selected from the group of: writing a logic state to the selected memory cell, and reading the selected memory cell; and a mode control circuit responsive to an external signal for adjusting the predetermined voltage or the predetermined time to perform an operation selected from the group consisting of: a partial read of the selected memory cell; a partial write of the selected memory cell; and applying ferroelectric stress to the memory cell. Preferably, the conducting lines comprise plate lines; the predetermined voltage comprises a plate line voltage; and the drive circuit comprises a plate line drive circuit. Preferably, the mode control circuit comprises a voltage control circuit for lowering the plate line voltage. Preferably, the conducting lines further include word lines for carrying a word line signal, and the mode control circuit comprises a timing control circuit for changing the timing of the word line signal. Preferably, the conducting lines comprise bit lines; the predetermined voltage comprises a precharge voltage; and the drive circuit comprises a bit line precharge circuit. Preferably, the mode control circuit comprises a voltage control circuit for raising the precharge voltage. Preferably, the conducting lines comprise sense amplifier voltage lines; the predetermined voltage comprises a sense amp voltage; and the drive circuit comprises a sense amplifier voltage drive circuit. Preferably, the conducting lines comprise a high sense amplifier voltage line and a low sense amplifier voltage line; the sense amplifier voltage includes a high sense amplifier voltage and a low sense amplifier voltage; and the mode control circuit comprises a voltage control circuit for narrowing the voltage window between the high sense amplifier voltage and the low sense amplifier voltage. Preferably, the conducting lines include word lines for carrying a word line signal and the mode control circuit comprises a timing control circuit for changing the timing of the word line signal.